[SOLVED] - LDO Voltage regulator getting hot - why?
Aug 5, 2022 · The circuit consists of a super capacitor, acting as the source, a variable output LDO voltage regulator, and a small DC motor. The voltage regulator chip is Semtech's SC4216HSETRT.
PTAT current source vs LDO to bias a ring oscillator for PVT ...
Apr 22, 2024 · I'm looking to minimize the frequency variation of an on-chip ring oscillator running at 2MHz, through using either an LDO as its supply voltage, or current-starving it with a current coming …
Negative Voltage Regulation using LDO in Cadence Virtuoso
May 12, 2024 · I have a negative rail -10V generated from a switched cap charge pump (CP) and want to regulate it. The rail varies +/-1V over the full load and have to stabilise to a specific voltage -7V. …
LDO design issue - no load condition | Forum for Electronics
Mar 27, 2019 · Hi I am working on a LDO design that requires a rather large PMOS pass transistor due to the specified max current. I have issues with pulling the pass transistor gate high enough at no …
What causes LDO output ripples? - Forum for Electronics
Aug 24, 2016 · Hi Everyone, I'm the beginner in the LDO design. I would like understand, what is actually causing the LDO output to have ripples when there is current load switching? In my …
overshoot undershoot during load transient analysis
Mar 5, 2021 · I have a question on the LDO load transient (P-Pass LDO, internally compensated). According to most of the literature, the voltage undershoot/overshoot with...
LDO phase margin? | Forum for Electronics
Jul 25, 2023 · Hi, I'm designing an LDO and will be using the output as VDD for digital logic. In this case, the output current will flow a large current of mA for a short period of time and then no current at all …
[SOLVED] - Input Power source selection for ESP32(LDO)
May 11, 2025 · Your bottom circuit should work, with std_match's suggested resistor from gate to ground, if the battery voltage never drops below the LDO minimum input voltage for 3.3V output. If …
Pass transistor in LDO | Forum for Electronics
Mar 14, 2012 · The PMOS pass transistor is not in saturation alll the time. why is it so.The gate input i fed is less than 1.5v. BTW Input to voltage regulator is 2-2.4. output should be 1.8v. so the table i ve …
LDO with NMOS as pass transistor.. | Forum for Electronics
Oct 18, 2004 · The NMOS pass transistor LDO is has a single pole roll-off characteristics.The gate of the NMOS pass transistor needs to be decoupled with capacitance to reduce the glitches in the output …